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<|diff_marker|> ADD A1000 <|file_sep|>// $Id: $ // File name: my_dma.h // Created: 11/25/2018 // Author: Jingwei Li // Lab Section: 337-04 // Version: 1.0 Initial Design Entry // Description: header file #ifndef MY_DMA_H_ #define MY_DMA_H_ #include "my_types.h" void my_dma_init( void ); void my_dma_send( u32 dest_addr,u32 src_addr,u32 size ); void my_dma_wait_done( void ); void my_dma_int_enable( void ); void my_dma_int_disable( void ); u32 my_dma_get_status( void ); #endif /* MY_DMA_H_ */ <|repo_name|>jw-li/ECE337<|file_sep|>/lab4/Assembly/main.asm ; Name: Jingwei Li ; E-mail: [email protected] ; Lab Section: 337-04 ; Assignment: Lab #4 Exercise #1 ; Date: 10/17/2018 ; Description: Write an assembly language program that uses two interrupt handlers. ; The first interrupt handler will toggle bit 0 of Port E (PE0). ; The second interrupt handler will toggle bit 1 of Port E (PE1). ; The main program should initialize all necessary registers, ; enable interrupts by setting SEI, ; set up interrupts by calling InitInterrupts(), ; set up PIE registers by calling InitPie(), ; then go into an infinite loop where it does nothing but wait. .ORIG x3000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; BEGINNING OF PROGRAM ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; LEA R0,AIRCR LDR R1,R0,#0 ;load R1 = R0[0] = AIRCR[0] AND R1,R1,#~(AIRCR_VECTKEY_MASK) ADD R1,R1,AIRCR_VECTKEY_VALUE ;R1 = (R1 & ~AIRCR_VECTKEY_MASK) + AIRCR_VECTKEY_VALUE = AIRCR[0] + AIRCR_VECTKEY_VALUE STR R1,R0,#0 ;store R1 into R0[0] = AIRCR[0] LEA R0,PRIORITY_MASKS ;load priority masks into R0 LDR R1,R0,#0 ;R1 = priority mask for PIECTRL register LDR R7,R0,#4 ;R7 = priority mask for PIEIER1 register LEA R5,PRIORITY_LEVELS ;load priority levels into R5 JSR INIT_INTERRUPTS ;set up Interrupt vectors JSR INIT_PIE ;set up PIE registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; MAIN PROGRAM LOOP ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; MAIN_LOOP BR MAIN_LOOP ;jump back to beginning of loop ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; INTERRUPT VECTORS FOR PIE GROUP 1 CHANNELS 1 AND 2 (COP AND RTI INTERRUPTS ARE ALREADY DEFINED) ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; .FILL x0008 ;Interrupt vector address offset for PIE GROUP 1 CHANNELS 1 AND 2 INTERRUPT_HANDLER_1_AND_2 PRESERVE_REGS TST IEERQ_RTI ;if IEERQ_RTI == TRUE jump to INT_HANDLER_RTI BRp INT_HANDLER_RTI TST IEERQ_COP ;if IEERQ_COP == TRUE jump to INT_HANDLER_COP BRp INT_HANDLER_COP TST IEERQ_1 ;if IEERQ_1 == TRUE jump to INT_HANDLER_1 BRp INT_HANDLER_1 TST IEERQ_2 ;if IEERQ_2 == TRUE jump to INT_HANDLER_2 BRp INT_HANDLER_2 RESTORE_REGS RTI ;return from interrupt service routine INT_HANDLER_RTI PRESERVE_REGS EINT ;set PE7 low so that this interrupt handler will not fire again until RTI flag is cleared by hardware RESTORE_REGS RTI ;return from interrupt service routine INT_HANDLER_COP PRESERVE_REGS EINT ;set PE7 low so that this interrupt handler will not fire again until COP flag is cleared by hardware RESTORE_REGS RTI ;return from interrupt service routine INT_HANDLER_1 PRESERVE_REGS TST PIEDACK_1 ;if PIEDACK_1 == TRUE jump to end BRp END_INT_HANDLER_1 SET PIEDACK_1 ;set PIEDACK_1 high so that this interrupt handler will not fire again until PIEACK_1 is set low by hardware EOR PE_PE0 ;toggles PE_PE0 = PE[0] SET PIEACK_1 ;set PIEACK_1 high so that this interrupt handler will fire again when necessary END_INT_HANDLER_1 RESTORE_REGS RTI ;return from interrupt service routine INT_HANDLER_2 PRESERVE_REGS TST PIEDACK_2 ;if PIEDACK_2 == TRUE jump to end BRp END_INT_HANDLER_2 SET PIEDACK_2 ;set PIEDACK_2 high so that this interrupt handler will not fire again until PIEACK_2 is set low by hardware EOR PE_PE1 ;toggles PE_PE1 = PE[1] SET PIEACK_2 ;set PIEACK_2 high so that this interrupt handler will fire again when necessary END_INT_HANDLER_2 RESTORE_REGS RTI ;return from interrupt service routine ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; END OF PROGRAM AND DATA SEGMENTS ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; AIRCR .FILL x05FA0004 ;bits [31..16] = AIRCR_VECTKEY_VALUE (write once) AIRCR_VECTKEY_MASK .FILL x00003FFF ;mask for bits [15..0] = {15..10} AIRCR_VECTKEY_VALUE .FILL x05FA ;bits [15..10] = AIRCR_VECTKEY_VALUE (write once) PRIORITY_MASKS .BLKW #6 ;priority masks (two bytes each) PRIORITY_LEVELS .BLKW #6 ;priority levels (one byte each) PRIORITY_MASKS+00 .FILL x00FF ;priority mask for PIECTRL register (two bytes) PRIORITY_MASKS+02 .FILL x0000 PRIORITY_MASKS+04 .FILL x00FF ;priority mask for PIEIER1 register (two bytes) PRIORITY_MASKS+06 .FILL x0000 PRIORITY_LEVELS+00 .FILL x00 ;priority level for PIECTRL register (one byte) PRIORITY_LEVELS+02 .FILL x01 ;priority level for PIEIER register (one byte) RTI_STATUS_FLAG .FILL x20 ;RTI status flag address offset COP_STATUS_FLAG .FILL x22 ;COP status flag address offset INTERRUPT_ACK_FLAG .FILL x24 ;interrupt acknowledge flag address offset RTEE_STATUS_FLAG .FILL x28 ;RTEE status flag address offset COP_CONTROL_FLAG .FILL x30 ;COP control flag address offset INTERRUPT_ENABLE_FLAG .FILL x38 ;interrupt enable flag address offset INTERRUPT_ENABLE_REGISTER .FILL x40008060 INTERRUPT_ENABLE_RTI_FLAG .FILL x01 INTERRUPT_ENABLE_COP_FLAG .FILL x02 INTERRUPT_ENABLE_GROUP_ONE_FLAGS .FILL xFC INTERRUPT_ACKNOWLEDGE_REGISTER .FILL x40008064 INTERRUPT_ACKNOWLEDGE_RTI_FLAG .FILL x01 INTERRUPT_ACKNOWLEDGE_COP_FLAG .FILL x02 INTERRUPT_ACKNOWLEDGE_GROUP_ONE_FLAGS .FILL xFC INTERRUPT_PRIORITY_CONTROL_REGISTER .FILL x40008070 PRIORITY_MASK_GROUP_ONE_FLAGS .FILL xFFFC INTERRUPT_PRIORITY_LEVEL_REGISTER .FILL x40008074 PRIORITY_LEVEL_GROUP_ONE_FLAGS .FILL xFFFC COP_CONTROL_REGISTER .FILL x40004040 COP_CONTROL_ENABLE_FLAG .FILL x01 PORT_E_DATA_DIRECTION_REGISTER_HIGH_BYTE .FILL x40008008 PORT_E_DATA_DIRECTION_REGISTER_LOW_BYTE .FILL x40008009 PORT_E_DATA_REGISTER_HIGH_BYTE .FILL x40008010 PORT_E_DATA_REGISTER_LOW_BYTE .FILL x40008011 PORT_E_DATA_REGISTER_INDEX_OFFSET_PORT_E_BIT_ZERO_HIGH_BYTE_OFFSET_PORT_E_BIT_ZERO_HIGH_BYTE_BIT_OFFSET_PORT_E_BIT_ZERO_HIGH_BYTE_BIT_NUMBER_PORT_E_BIT_ZERO_HIGH_BYTE_BIT_NUMBER_HIGH_BYTE_PORT_E_BIT_ZERO_HIGH_BYTE_BIT_NUMBER_LOW_BYTE_PORT_E_BIT_ZERO_HIGH_BYTE_BIT_NUMBER_LOW_BYTE_PORT_E_BIT_ZERO_HIGH_BYTE_BIT_NUMBER_LOW_BYTE_SHIFT_AMOUNT_PORT_E_BIT_ZERO_HIGH_BYTE_SHIFT_AMOUNT_SHIFT_AMOUNT_HIGH_BYTE_SHIFT_AMOUNT_LOW_BYTE_SHIFT_AMOUNT_LOW_BYTE_PORT_E_BIT_ZERO_HIGH_BYTE_MASK_PORT_E_BIT_ZERO_HIGH_BYTE_MASK_PORT_E_BIT_ZERO_HIGH_BYTE_MASK_LOW_BYTE_PORT_E_BIT_ZERO_HIGH_BYTE_MASK_LOW_BYTE_SHIFT_AMOUNT_PORT_E_BIT_ZERO_HIGH_BYTE_SHIFT_AMOUNT_PORT_E_BIT_ZERO_HIGH_BYTE_CLEAR_VALUE_PORT_E_BIT_ZERO_HIGH_BYTE_CLEAR_VALUE_LOW_BYTE_PORT_E_BIT_ZERO_HIGH_BYTE_CLEAR_VALUE_LOW_BYTE_SHIFT_AMOUNT_PORT_E_BIT_ZERO_HIGH_BYTE_SHIFT_AMOUNT_CLEAR_VALUE_SHIFT_AMOUNT_HIGH_BYTE_CLEAR_VALUE_SHIFT_AMOUNT_LOW_BYTE_SHIFT_AMOUNT_LOW_BYTE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE_SET_VALUE SET VALUE SET VALUE SHIFT AMOUNT SHIFT AMOUNT HIGH BYTE SHIFT AMOUNT LOW BYTE CLEAR VALUE SHIFT AMOUNT HIGH BYTE CLEAR VALUE SHIFT AMOUNT LOW BYTE PORT E BIT ZERO HIGH BYTE ADDRESS OFFSET PORT E BIT ZERO HIGH BYTE ADDRESS OFFSET PORT E BIT ZERO HIGH BYTE ADDRESS OFFSET HIGH BYTE PORT E BIT ZERO HIGH BYTE ADDRESS OFFSET LOW BYTE PORT E BIT ZERO HIGH BYTE ADDRESS OFFSET LOW BYTE PORT E BIT ZERO HIGH BYTE BIT NUMBER PORT E BIT ZERO HIGH BYTE BIT NUMBER PORT E BIT ZERO HIGH